The advent of Ultra Large Scale Integrated (ULSI) circuits have allowed semiconductor manufacturers worldwide to fabricate semiconductor devices to an extremely compact dimensions. The formation of semiconductor devices involves the process of fabrication which provides isolation within the semiconductor device. In order to fabricate integrated circuits (ICs), devices isolated from one another must first be formed in the silicon substrate. In fabrication of a ULSI, a small amount of leakage in a device can induce significant power dissipation for the overall circuit.
Trench isolation is used primarily for isolating devices in VLSI and ULSI, and hence they can be considered as replacement for conventional LOCOS isolation. Shallow trench isolation has gained popularity for in compact semiconductor dimensions such as quarter-micron technology. In a basic shallow trench isolation (STI) technology, shallow trenches are anisotropically etched into the silicon substrate. A CVD oxide is deposited onto the substrate and is then planarized by CMP (Chemical Mechanical Polishing) or etching back. Another approach to shallow trench isolation is called a Buried Oxide with Etch-Stop process (BOXES). The process uses a silicon-nitride etch-stop layer and a pad layer formed on the substrate before the CVD-oxide is deposited.
As shown in FIG. 1, on a silicon substrate 1, problems associated with the formation of STI include dishing effect 3 of wide trench, erosion of small nitride area, and oxide 4 remaining on large nitride area 6. The dishing effect degrades the planarity of a layer, and impacts the control of implantation during the implantation process. Isolated devices are fabricated in the area denoted by 2, silicon nitride may erode the area completely. This will damage the silicon substrate 1 and devices that are fabricated here. The oxide 4 that remains on the silicon nitride layer makes wet strip of silicon nitride unlikely.
Turning to FIG. 2, a pad oxide layer 5 and a silicon nitride layer 7 are respectively formed on a silicon substrate 1. In order to overcome the aformentioned problems during the formation of shallow trench isolation, a plurality of protrudent portions of the silicon oxide 9 are generated over the trench region. This structure is referred to as "reverse tone". The protruded portions can eliminate the dishing problem due to the removing rate of the CMP performed over the trench is faster than the neighboring regions.
However, conventional methods cause micron trench in a silicon nitride layer during a step of etching for forming the "reverse tone". Turning to FIG. 3, a photoresist 12 is patterned on the oxide layer 9 used to form the "reverse tone". A micron trench 10 is generated in the silicon nitride layer 7. The silicon nitride layer 7 may be removed during a subsequent step of STI CMP.